1. Field of the Invention
The present invention relates to a semiconductor device, particularly, to a MIS (Metal-Insulator-Semiconductor) type semiconduct device with an improved structure in the gate insulating film.
2. Description of the Related Art
In recent years, large scale integration (LSI) circuits are used in many cases in electronic computers, communication equipments, etc. the LSI is prepared by integrating a large number of transistors on a semiconductor substrate several millimeters square. The degree of integration has been further promoted recently for enabling LSI to perform many additional functions.
MIS type field effect transistors (MISFET) are main constituents of a silicon semiconductor integrated circuit of the most promoted degree of integration such as DRAM. FIG. 13 shows the general construction of, for example, an n-MISFET. As seen from the drawing, a gate electrode 154 consisting of a metal or a polycrystalline silicon is formed on a p-type silicon substrate 151 with an insulating film 153 consisting of, for example, silicon dioxide, interposed therebetween. Further, n-type source and drain regions 152a, 152b are formed in a substrate surface region such that the source and drain regions are positioned at the both sides of the region below the gate electrode. If voltage is applied to the gate electrode, an n-type channel is induced in the substrate surface region between the source and drain regions. At the same time, the current flowing through the channel is controlled by the voltage applied to the gate electrode. In order to promote the degree of integration and to achieve a high speed operation of the integrated circuit, miniaturization of the transistor constructed as shown in FIG. 13 is on a rapid progress. As a matter of fact, an element having an effective channel length of 0.1 micron has already been developed.
If the element is miniaturized on the basis of the scaling theory, which determines the shape of the element, the thickness of the gate insulating film 153 is rendered as small as at most 10 nm in the case where the gate length is set at 0.5 micron. Where the FET comprises such a thin gate insulating film, a high electric field is applied to the lower corner portions of the gate electrode 154 during the operation of the FET, leading to reduction in the breakdown voltage between the lower corner portions of the gate electrode 154 and each of the source and drain regions 152a, 152b, i.e., reduction in the gate breakdown voltage, and further to an insulation breakdown.
The arrows shown in FIG. 13 denote lines of electric force. The length of the arrow represents the intensity of the electric field. Needless to say, the longer arrow denotes the stronger electric field. As apparent from FIG. 13, electric field strength is particularly prominent in the lower corner portions of the gate electrode 154, with the result that current leakage tends to take place in the lower corner portions of the gate electrode 154 so as to bring about reduction in the gate breakdown voltage.
FIG. 14 illustrates a conventional measure for dealing with the difficulty noted above. As shown in the drawing, the gate oxide film 153 consisting of silicon dioxide is formed on the silicon substrate 151. Further, the gate electrode 154 consisting of polycrystalline silicon is formed on the gate oxide film 153. The element further comprises the drain region 152b and a channel region 152c. In the conventional technique, heating under an oxidizing atmosphere is applied after formation of the gate electrode 154 so as to cause growth of the oxide film below the lower corner portion of the gate electrode 154, i.e., to increase the thickness of the oxide film in a portion 153a. Needless to say, the thickness of the oxide film portion 153a is increased in an attempt to prevent the reduction in the gate breakdown voltage. In this technique, however, the thick portion of the oxide film 153 is positioned to reach a region below the central portion of the gate electrode in accordance with reduction in the gate length accompanying a further progress in the miniaturization of the element, with the result that the gate electrode fails to control as desired the potential of the channel region.
It should also be noted that, in a fine MISFET, the electric field in the lateral direction is intensified in general across the junction between the drain region and the channel region so as to generate carriers having a high energy level. In many cases, the carriers thus generated are injected into the insulating film. As a result, some portions where carriers are likely to be trapped are formed in the insulating film. Also, interface states at which the carriers are likely to be trapped are generated on the interface between the semiconductor substrate and the insulating film. It follows that the element is rendered unsatisfactory in terms of reliability of operation. For overcoming the difficulty, proposed is an FET structure achieved by improving the impurity profile in the drain region, so called the LDD (Lightly Doped Drain) structure. As a matter of fact, the particular FET structure is actually employed in a MISFET.
FIG. 15 shows a cross section of a conventional MISFET employing the LDD structure noted above. As shown in the drawing, an n.sup.+ -type source region 162a and an n.sup.+ -type drain region 162b are formed in the surface region of a p-type silicon substrate 161. Also, n-type regions 163a, 163b having an impurity concentration lower than that in the source and drain regions 162a, 162b are formed in the surface region of the substrate 161 between and in direct contact with the source and drain regions 162a, 162b, respectively, such that these n-type regions 163a, 163b are apart from each other. A channel region 164 is interposed between the n-type regions 163a and 163b. Further, a gate insulating film 165 is formed on the channel region, and a gate electrode 166 is formed on the gate insulating film 165. It should also be noted that side walls 167a, 167b are formed on the side of the source region and the drain region, respectively, in a manner to cover the side surfaces of the gate insulating film 165 and the gate electrode 166. Also, electrode wirings 168a, 168b are connected to the source region 162a and the drain region 162b, respectively. Further, the clearances between the electrode wirings 168a, 168b and the side walls 167a, 167b of the source and drain regions are completely filled with an insulating layer 169. As apparent from the drawing, the insulating layer 169 extends to cover the upper surface of the gate electrode 166.
It is important to note that the n-type region 163a, 163b are included in the MISFET of the construction shown in FIG. 15. As a result, the depletion layer is expanded during the operation of the element, making it possible to moderate the electric field applied to the particular region. However, the MISFET employing the LDD structure gives rise to another problem. Specifically, the impurity concentration of the n-type region 163a, 163b formed in direct contact with the source and drain region 162a, 162b is so low and is not controlled by the gate electrode 166. As a result, a parasitic resistance is increased, leading to a diminished drivability. If the side walls 167a, 167b of the gate structure are formed of a material having a dielectric constant higher than that of the gate insulating film 165 in an attempt to improve the control capability of the gate electrode, however, the electric field strength is promoted in the lower corner portion 166a of the gate electrode 166, resulting in reduction in the gate breakdown voltage
As described above, a strong electric field is applied to the lower corner portion of the gate electrode in the conventional semiconductor device, e.g., MISFET, of a high integration density, leading to reduction in the gate breakdown voltage and, further, to insulation breakdown. In the technique intended to overcome the above-noted difficulty, the control capability of the gate electrode is impaired.